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note : all information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publi cation; however, this data sheet cannot be a ?controlled document?. current revisions, if any, to these specifications are maintained at the factory and are available upon your request. we recommend checking the revision level befor e finalization of your design documentation. ? 2001 elantec semiconductor, inc. e l 5 4 8 5 c , e l 5 4 8 6 c - p r e l i m i n a r y general description the el5485c and el5486c comparators are designed for operation in single supply and dual supply applications with 5v to 12v between v s + and v s -. for single supplies, the inputs can operate from 0.1v below ground for use in ground sensing applications. the output side of the comparators can be supplied from a single sup- ply of 2.7v to 5v. the rail-to-rail output swing enables direct connection of the comparator to both cmos and ttl logic circuits. the latch input of the el5485c and el5486c can be used to hold the comparator output value by applying a low logic level to the pin. the el5485c is available in the 16-pin so package and the el5486c in the 24-pin qsop package. both are specified for operation over the full -40c to +85c temperature range. also available are single (el5185c), dual (el5285c) , and window comparator (el5287c) versions . pin configurations 1 2 3 4 16 15 14 13 5 6 7 12 11 10 8 9 el5485cs (16-pin so) 1 2 3 4 16 15 14 13 5 6 7 12 11 9 8 10 20 19 18 17 24 23 22 21 EL5486CU (24-pin qsop) - + - + - + - + ina- ina+ gnd outa outb vs- inb+ inb- ind- ind+ vs+ outd outc vsd inc+ inc- - + - + - + - + latcha outa outb latchb vs- nc inb+ inb- latchd outd outc latchc vsd nc inc+ inc- ina- ina+ nc gnd ind- ind+ nc vs+ features ? 4ns typ. propagation delay ? 5v to 12v input supply ? +2.7v to +5v output supply ? true-to-ground input ? rail-to-rail outputs ? separate analog and digital supplies ? active low latch ? single (el5185c) available ? dual (el5285c) available ? window available (el5287c) ? pin-compatible 8ns family available (el5x81c, el5283c & el5482c) applications ? threshold detection ? high speed sampling circuits ? high speed triggers ? line receivers ? pwm circuits ? high speed v/f converters ordering information part no package tape & reel outline # el5485cs 16-pin so - mdp0027 el5485cs-t7 16-pin so 7? mdp0027 el5485cs-t13 16-pin so 13? mdp0027 EL5486CU 24-pin qsop - mdp0040 EL5486CU-t13 24-pin qsop 13? mdp0040 el5485c, el5486c - preliminary quad 4ns high speed comparators s e p t e m b e r 7 , 2 0 0 1
2 el5485c, el5486c - preliminary quad 4ns high speed comparators e l 5 4 8 5 c , e l 5 4 8 6 c - p r e l i m i n a r y absolute maximum ratings (t a = 25c) absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device operation is not implied analog supply voltage (v s + to v s -) + 12.6 v digital supply voltage (v sd to gnd) +7v differential input voltage [(v s -) -0.2v] to [(v s +) +0.2v] common-mode input voltage [(v s -) -0.2v] to [(v s +) +0.2v] latch input voltage -0.2v to [(v sd ) +0.2v] storage temperature range -65c to +150c ambient operating temperature -40c to +85c operating junction temperature 125c power dissipation tbdmw esd voltage 2kv important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unless otherwise note d, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a . electrical characteristics v s = 5v, v sd = 5v, r l = 2.3k w , c l = 15pf, t a = 25c, unless otherwise specified. parameter description condition min typ max unit input v os input offset voltage v cm = 0v, v o = 2.5v 1 4 mv i b input bias current -10 -5 a c in input capacitance 5 pf i os input offset current v cm = 0v, v o = 2.5v -2.5 0.5 2.5 a v cm input voltage range (v s -) - 0.1 (v s +) - 2.25 v cmrr common-mode rejection ratio -5v < v cm < +2.75v, v o = 2.5v -65 -90 db output v oh output high voltage v in > 250mv v sd - 0.6 v sd - 0.4 v v ol output low voltage v in > 2 50mv gnd + 0.25 gnd + 0.5 v dynamic performance t pd + latch disable to high delay v in = 1v p-p , v od = 50mv 4 6 ns t pd - latch disable to low delay v in = 1v p-p , v od = 50mv 4 6 ns supply i s + positive analog supply current (per comparator) 12 13 ma i s - negative analog supply current (per comparator) 7.5 8.5 ma i sd digital supply current (per comparator) all inputs high 5.5 6.5 ma (per comparator) all inputs low 0.9 1.2 ma psrr power supply rejection ratio -60 -80 db latch v lh latch input voltage high 2.0 v v ll latch input voltage low 0.8 v i lh latch input current high v lh = 3.0v -30 -18 a i ll latch input current low v ll = 0.3v -30 -24 a t d + positive going delay time v od = 5mv, c l = 15pf, i o = 2ma 4 ns t d - negative going delay time v od = 5mv, c l = 15pf, i o = 2ma 4 ns t s minimum setup time 2 ns t h minimum hold time 1 ns t pw (d) minimum latch disable pulse width 5 ns
3 el5485c, el5486c - preliminary quad 4ns high speed comparators e l 5 4 8 5 c , e l 5 4 8 6 c - p r e l i m i n a r y typical performance curves supply current vs supply voltage (per comparator) 0 1 2 3 4 5 6 10 8 6 4 2 0 v s (v) i s ( m a ) i s + i s - v in =50mv r l =2.2k offset voltage vs temperature -50 -30 10 30 50 70 90 3 2.5 1.5 1 0.5 0 temperature (c) v o s ( m v ) 2 -10 output high voltage vs temperature -50 -30 10 30 50 70 90 4.832 4.83 4.826 4.822 4.82 4.818 temperature (c) v o h ( v ) 4.828 4.824 -10 input bias current vs temperature -50 -30 30 50 90 8 7 3 2 1 0 temperature (c) i b ( a ) 5 -10 10 70 6 4 propagation delay vs overdrive v in =5v step 0.2 0.6 1 1.4 1.8 2.2 2.6 7.8 7.4 7 6.8 6.6 6.4 v od (v) d e l a y t i m e ( n s ) propagation delay vs source resistance v in =1v step 0 1.6 2 15 5 source resistance (k w ) d e l a y t i m e ( n s ) 13 7.6 7.2 t pd - t pd + v s =5v v sd =5v r l =2.2k 0.4 1.2 0.8 11 7 9 v s =5v v sd =5v v od =50mv r l =2.2k t pd - t pd +
4 el5485c, el5486c - preliminary quad 4ns high speed comparators e l 5 4 8 5 c , e l 5 4 8 6 c - p r e l i m i n a r y typical performance curves propagation delay vs supply voltage 4 4.2 4.8 5.2 5.4 5.6 6 6.8 6.6 6.2 6 5.8 5.6 v s (v) d e l a y t i m e ( n s ) 6.4 4.4 digital supply current vs switching frequency (per comparator) 0 20 40 50 25 20 10 0 frequency (mhz) i s d ( m a ) 15 10 5 30 t pd - t pd + v sd =v s + v od =50mv r l =2.2k 5 4.6 5.8 v s =5v t a =25c v sd =5v v sd =3v output low voltage vs temperature -50 -30 10 30 50 70 90 0.285 0.235 temperature (c) v o l ( v ) -10 0.275 0.255 0.245 0.265 supply current vs temperature (per comparator) -50 10 70 90 12 11 8 6 temperature (c) s u p p l y c u r r e n t ( m a ) -30 7 50 10 9 30 -10 i s + i s - propagation delay vs overdrive v in =1v step 50 100 250 300 400 500 600 6.1 6 5.8 5.5 5.2 v od (mv) d e l a y t i m e ( n s ) 5.9 5.7 150 5.6 5.4 5.3 350 450 550 200 t pd - t pd + v s =5v v sd =5v r l =2.2k propagation delay vs overdrive v in =3v step 0.2 0.6 0.8 1.2 1.6 2 8 6.5 5 v od (mv) d e l a y t i m e ( n s ) 7.5 7 6 5.5 1 1.4 1.8 0.4 t pd - t pd + v s =5v v sd =5v r l =2.2k
5 el5485c, el5486c - preliminary quad 4ns high speed comparators e l 5 4 8 5 c , e l 5 4 8 6 c - p r e l i m i n a r y typical performance curves output with 50mhz input v in =1v p-p output with 50mhz input v in =3v p-p output (5ns/div, 2v/div) input (5ns/div, 0.5nv/div) output (5ns/div, 2v/div) input (5ns/div, 2v/div) propagation delay vs load capacitance v in =1v step 0 10 30 40 50 80 100 9 5 c load (pf) d e l a y t i m e ( n s ) 20 8.5 6.5 5.5 7.5 8 6 7 60 90 70 v s =5v v sd =5v v od =50mv r l =2.2k t pd - t pd + 1087mw q s o p 2 4 1 1 5 c / w power dissipation vs ambient temperature 1.4 0 1 0.6 0.4 0.2 p o w e r d i s s i p a t i o n ( w ) 1.2 0.8 0 125 100 75 50 25 ambient temperature (c) 150 85 909mw s o 1 6 q j a = 1 1 0 c / w
6 el5485c, el5486c - preliminary quad 4ns high speed comparators e l 5 4 8 5 c , e l 5 4 8 6 c - p r e l i m i n a r y timing diagram v in v od t h t s t pd - t pw (d) t d + latch enable input latch compare latch latch compare differential input voltage comparator output 1.4v v os 2.4v definition of terms term definition v os input offset voltage - voltage applied between the two input terminals to obtain cmos logic threshold at the output v in input voltage pulse amplitude - usually set to 1v for comparator specifications v od input voltage overdrive - usually set to 50mv and in opposite polarity to vin for comparator specifications t pd + input to output high delay - the propagation delay measured from the time the input signal crosses the input offset voltage to t he cmos logic threshold of an output low to high transition t pd - input to output low delay - the propagation delay measured from the time the input signal crosses the input offset voltage to th e cmos logic threshold of an output high to low transition t d + latch disable to output high delay - the propagation delay measured from the latch signal crossing the cmos threshold in a low t o high transition to the point of the output crossing cmos threshold in a low to high transition t d - latch disable to output low delay - the propagation delay measured from the latch signal crossing the cmos threshold in a low to high transition to the point of the output crossing cmos threshold in a high to low transition t s minimum setup time - the minimum time before the negative transition of the latch signal that an input signal change must be pre sent in order to be acquired and held at the outputs t h minimum hold time - the minimum time after the negative transition of the latch signal that an input signal must remain unchange d in order to be acquired and held at the output t pw (d) minimum latch disable pulse width - the minimum time that the latch signal must remain high in order to acquire and hold an inpu t signal change
7 el5485c, el5486c - preliminary quad 4ns high speed comparators e l 5 4 8 5 c , e l 5 4 8 6 c - p r e l i m i n a r y pin descriptions el5485c 16-pin so (0.150") el5486c 24-pin qsop pin name function equivalent circuit 1 1 ina- negative input, channel a circuit 1 2 2 ina+ positive input, channel a (reference circuit 1) 3,10,15,22 nc not connected 3 4 gnd digital ground 5 latcha latch input, channel a circuit 2 4 6 outa output, channel a circuit 3 5 7 outb output, channel b (reference circuit 3) 8 latchb latch input, channel b (reference circuit 2) 6 9 vs- negative supply voltage 7 11 inb+ positive input, channel b (reference circuit 1) 8 12 inb- negative input, channel b (reference circuit 1) 9 13 inc- negative input, channel c (reference circuit 1) 10 14 inc+ positive input, channel c (reference circuit 1) 11 16 vsd digital supply voltage 17 latchc latch input, channel c (reference circuit 2) 12 18 outc output, channel c (reference circuit 3) 13 19 outd output, channel d (reference circuit 3) 20 latchd latch input, channel d (reference circuit 2) in+ in- v s + v s - v sd v s + v s - latch v sd v s + v s - out
8 el5485c, el5486c - preliminary quad 4ns high speed comparators e l 5 4 8 5 c , e l 5 4 8 6 c - p r e l i m i n a r y 14 21 vs+ positive supply voltage 15 23 ind+ positive input, channel d (reference circuit 1) 16 24 ind- negative input, channel d (reference circuit 1) pin descriptions el5485c 16-pin so (0.150") el5486c 24-pin qsop pin name function equivalent circuit
9 el5485c, el5486c - preliminary quad 4ns high speed comparators e l 5 4 8 5 c , e l 5 4 8 6 c - p r e l i m i n a r y applications information power supplies and circuit layout the el5485c and el5486c comparators operate with single and dual supply with 5v to 12v between v s + and v s -. the output side of the comparator is supplied by a single supply from 2.7v to 5v. the rail to rail output swing enables direct connection of the comparator to both cmos and ttl logic circuits. as with many high speed devices, the supplies must be well bypassed. elan- tec recommends a 4.7f tantalum in parallel with a 0.1f ceramic. these should be placed as close as possi- ble to the supply pins. keep all leads short to reduce stray capacitance and lead inductance. this will also minimize unwanted parasitic feedback around the com- parator. the device should be soldered directly to the pc board instead of using a socket. use a pc board with a good, unbroken low inductance ground plane. good ground plane construction techniques enhance stability of the comparators. input voltage considerations the el5485c and el5486c?s input range is specified from 0.1v below v s - to 2.25v below v s +. the criterion for the input limit is that the output still responds cor- rectly to a small differential input signal. the differential input stage is a pair of pnp transistors, therefore, the input bias current flows out of the device. when either input signal falls below the negative input voltage limit, the parasitic pn junction formed by the substrate and the base of the pnp will turn on, resulting in a significant increase of input bias current. if one of the inputs goes above the positive input voltage limit, the output will still maintain the correct logic level as long as the other input stays within the input range. however, the propa- gation delay will increase. when both inputs are outside the input voltage range, the output becomes unpredict- able. large differential voltages greater than the supply voltage should be avoided to prevent damages to the input stage. input slew rate most high speed comparators oscillate when the voltage of one of the inputs is close to or equal to the voltage on the other input due to noise or undesirable feedback. for clean output waveform, the input must meet certain min- imum slew rate requirements. in some applications, it may be helpful to apply some positive feedback (hyster- esis) between the output and the positive input. the hysteresis effectively causes one comparator's input voltage to move quickly past the other, thus taking the input out of the region where oscillation occurs. for the el5485c and el5486c, the propagation delay increases when the input slew rate increases for low overdrive voltages. with high overdrive voltages, the propagation delay does not change much with the input slew rate. latch pin dynamics the el5486c contains a ?transparent? latch for each channel. the latch pin is designed to be driven with either a ttl or cmos output. when the latch is con- nected to a logic high level or left floating, the comparator is transparent and immediately responds to the changes at the input terminals. when the latch is switched to a logic low level, the comparator output remains latched to its value just before the latch?s high- to-low transition. to guarantee data retention, the input signal must remain the same state at least 1ns (hold time) after the latch goes low and at least 2ns (setup time) before the latch goes low. when the latch goes high, the new data will appear at the output in approximately 6ns (latch propagation delay). the el5485c does not have latch inputs. hysteresis hysteresis can be added externally. the following two methods can be used to add hysteresis. inverting comparator with hysteresis: r 3 adds a portion of the output to the threshold set by r 1 and r 2 . the calculation of the resistor values are as follows: + - r 3 v in v ref r 2 r 1
10 el5485c, el5486c - preliminary quad 4ns high speed comparators e l 5 4 8 5 c , e l 5 4 8 6 c - p r e l i m i n a r y select the threshold voltage v th and calculate r 1 and r 2 . the current through r 1 /r 2 bias string must be many times greater than the input bias current of the comparator: let the hysteresis be v h , and calculate r 3 : where: v o =v sd -0.8v (swing of the output) recalculate r 2 to maintain the same value of v th : non inverting comparator with hysteresis: r 3 adds a portion of the output to the positive input. note that the current through r 3 should be much greater than the input bias current in order to minimize errors. the calculation of the resistor values as follows: pick the value of r 1 . r 1 should be small (less than 1k w ) in order to minimize the propagation delay time. choose the hysteresis v h and calculate r 3 : check the current through r 3 and make sure that it is much greater than the input bias current as follows: the above two methods will generate hysteresis of up to a few hundred millivolts. beyond that, the impedance of r 3 is low enough to affect the bias string and adjustment of r 1 may be required. power dissipation when switching at high speeds, the comparator's drive capability is limited by the rise in junction temperature caused by the internal power dissipation. for reliable operation, the junction temperature must be kept below t jmax (125c). an approximate equation for the device power dissipa- tion is as follows. assume the power dissipation in the load is very small: where: v s is the analog supply voltage from v s + to v s - i s is the analog quiescent supply current per comparator v sd is the digital supply voltage from v sd to ground i sd is the digital supply current per comparator i sd strongly depends on the input switching frequency. please refer to the performance curve to choose the input driving frequency. having obtained the power dissipa- tion, the maximum junction temperature can be determined as follows: where: t max is the maximum ambient temperature q ja is the thermal resistance of the package threshold detector the inverting input is connected to a reference voltage and the non-inverting input is connected to the input. as the input passes the v ref threshold, the comparator's v th v ref r 1 r 1 r 2 + ------------------- = r 3 v o v h -------- r 1 ( r 2 ) || = r 2 1v ref ( v th ) v th r 1 ----------- ? ? ? ? v th 0.5v sd ? r 3 ------------------------------------- ? ? + = + - r 3 v in v ref r 1 r 3 v ( sd 0.8 ) r 1 v h -------- ? = i 0.5v sd v ref ? r 3 ---------------------------------------- = p diss v s i s v sd i sd ) + ( = t jmax t max q ja p diss + =
11 el5485c, el5486c - preliminary quad 4ns high speed comparators e l 5 4 8 5 c , e l 5 4 8 6 c - p r e l i m i n a r y output changes state. the non-inverting and inverting inputs may be reversed. crystal oscillator a simple crystal oscillator using one comparator of an el5485c and el5486c is shown below. the resistors r 1 and r 2 set the bias point at the comparator's non- inverting input. resistors r 3 , r 4 , and c 1 set the invert- ing input node at an appropriate dc average voltage based on the output. the crystal's path provides resonant positive feedback and stable oscillation occurs. although the el5485c and el5486c will give the cor- rect logic output when an input is outside the common mode range, additional delays may occur when it is so operated. therefore, the dc bias voltages at the inputs are set about 500mv below the center of the common mode range and the 200 w resistor attenuates the feed- back to the non-inverting input. the circuit will operate with most at-cut crystal from 1mhz to 8mhz over a 2v to 7v supply range. the output duty cycle for this circuit is roughly 50% at 5v v cc , but it is affected by the tolerances of the resistors. the duty cycle can be adjusted by changing v cc value. + - v in v ref v out + - 200 w v out r 4 r 3 5v 1mhz to 8mhz 2k w c 1 0.01f 5k w 1.5k w 2k w r 1 r 2
12 el5485c, el5486c - preliminary quad 4ns high speed comparators e l 5 4 8 5 c , e l 5 4 8 6 c - p r e l i m i n a r y general disclaimer specifications contained in this data sheet are in effect as of the publication date shown. elantec, inc. reserves the right to make changes in the cir- cuitry or specifications contained herein at any time without notice. elantec, inc. assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. warning - life support policy elantec, inc. products are not authorized for and should not be used within life support systems without the specific written consent of elantec, inc. life support systems are equipment intended to sup- port or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death. users con- templating application of elantec, inc. products in life support systems are requested to contact elantec, inc. factory headquarters to establish suitable terms & conditions for these applications. elan- tec, inc.?s warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages. s e p t e m b e r 7 , 2 0 0 1 printed in u.s.a. elantec semiconductor, inc. 675 trade zone blvd. milpitas, ca 95035 telephone: (408) 945-1323 (888) elantec fax: (408) 945-9305 european office: +44-118-977-6020 japan technical center: +81-45-682-5820

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